Several methods have been developed for creating thin films on substrates used in manufacturing semiconductor devices. Among the more established techniques is Chemical Vapor Deposition (CVD). Atomic Layer Deposition (ALD), also referred to Molecular Layer Deposition (MLD), a variant of CVD, is a relatively newer technology now emerging as a potentially superior method of achieving uniform, conformal film deposition. ALD has demonstrated an outstanding ability to maintain ultra-uniform thin deposition layers over complex topology. This is at least partially true because ALD is not as flux dependent as is CVD. This flux-independent nature of ALD allows processing at lower temperatures than with conventional CVD methods.
The technique of ALD is based on the principle of the formation of a saturated monolayer of reactive precursor molecules by chemisorption. A typical ALD process for forming an AB film, for example, on a substrate consists of injecting a precursor or reactant A (RA) for a period of time in which a saturated monolayer of A is formed on the substrate. Then, the precursor or reactant A (RA) is purged from the chamber using an inert gas, GI. This is followed by injecting precursor or reactant B (RB) into the chamber, also for a period of time, to combine B with A, thus forming the layer AB on the substrate. Then, the precursor or reactant B (RB) is purged from the chamber. This process of introducing precursor or reactant A (RA), purging the reactor, introducing precursor or reactant B (RB), and purging the reactor can be repeated a number of times to achieve an AB film of a desired thickness.
In the semiconductor industry, the minimum feature sizes of microelectronic devices are well into the deep sub-micron regime to meet the demand for faster and lower power semiconductor devices. The downscaling of complimentary metal-oxide-semiconductor (CMOS) devices imposes scaling constraints on the gate dielectric material. The thickness of the conventional SiO2 gate dielectric is approaching its physical limits. The most advanced devices are using nitrided SiO2 gate dielectrics approaching equivalent oxide thickness (EOT) of about 1 nanometer (nm) or less where leakage current density can be as much as 1 mA/cm2. To improve device reliability and reduce electrical leakage from the gate dielectric to the transistor channel during operation of the device, semiconductor transistor technology is planning on using high dielectric constant (high-k) gate dielectric materials that allow increased physical thickness of the gate dielectric layer while maintaining a low equivalent oxide thickness (EOT). Equivalent oxide thickness is defined as the thickness of SiO2 that would produce the same capacitance as that obtained form an alternate dielectric material.
Dielectric materials featuring a dielectric constant greater than that of SiO2 (k˜3.9) are commonly referred to as high-k materials. High-k materials may refer to dielectric materials that are deposited onto substrates (e.g., HfO2, ZrO2, HfSiO, ZrSiO, etc.) rather than grown on the surface of a substrate, as can be the case for SiO2. High-k materials may incorporate a metal oxide layer or a metal silicate layer, e.g., Ta2O5 (k˜26), TiO2 (k˜80), ZrO2 (k˜25), AlN, (k˜9), Al2O3 (k˜9), HfSiO (k˜5-20), and HfO2 (k˜25).
These exemplary high-k materials, and nanolaminates thereof, can be used in many logic and memory devices where the scaling of SiO2 is no longer practical. Films of high-k materials often need to be relatively thin, for example less than about 50 angstrom (A). This requires the films to have good physical properties such as smooth film interfaces and good film uniformity across the wafer. In addition, good electrical properties such as low film interface trap densities, high dielectric constant, low hysteresis and low leakage currents are required for integration into semiconductor devices.